1. Field of the Invention
The invention relates to a digital data apparatus comprising a data processing unit and a plurality of peripheral units, said data processing unit and said peripheral units being connected to a data bus for the transfer of digital data, said data processing unit being also connected to an address bus which comprises at least as many address lines as there are peripheral units, each peripheral unit is directly connected to said data processing unit by means of at least one of said address lines for selectively addressing said peripheral unit, each peripheral unit includes a dedicated storage location for storing a multi-bit identification code which identifies uniquely that peripheral unit. Commonly, a processing unit is implemented as an integrated circuit in a package, with connection to one or more peripheral units (for example, RAM's) external to the integrated circuit package being effected by way of external connecting pins on the package.
2. Description of the Prior Art
A prior art example of digital data apparatus of the above character is given in IBM Technical Disclosure Bulletin, Vol. 18, No. 3, August 1975, pages 878/9 in the article "Basic Storage Module Selection Check". In this article, a "command" signal is issued to a particular BSM (Basic Storage Module) by transmitting that "command" signal over a transfer bus to that BSM (and possibly other BSM's), and activating the particular BSM by a "command select" signal applied to that BSM only. The "command" signal includes a module address which is stored in an identified portion of each BSM to which the "command" signal is applied. The module address is also decoded by a system controller to produce the unique "command select" signal for the BSM. On receipt of the "command select" signal the BSM concerned compares the stored identifier portion with a pre-stored identification code. The "command" signal is executed or not according as the identifier portion matches or does not match the identification code. With such an implementation, it may be a first requirement to accommodate connection between the processing unit and different numbers of memory units, according to particular uses of the apparatus, and it may be a second requirement to allow connection of memory units in various different configurations. To achieve the first of these requirements it becomes necessary, in order to prevent any attempt by the processing unit to transfer data to a non-existent memory unit, for the processing unit to know which memory unit addresses are valid for selectively addressing memory units because respective memory units have been provided in respect of them, and which memory unit addresses are invalid because no memory units have been provided in respect of them. In a specific implementation of the digital data apparatus a unique multi-bit identification code is recorded in a storage location in each of a plurality of memory units, and this code is used by interrogation means for detecting the presence or absence of a memory unit corresponding to any memory unit address used by the processing unit to address the memory units. This detection can be effected by making the identification code for a memory unit code but one or more further units also. Such address codes are therefore considered to be invalid for the simpler configurations because they can select more than one memory or other peripheral unit, and can thus cause possible conflicts and hence corrupted data in the transfer to the processing unit.
It is a further object of the present invention to provide means of avoiding the use of this latter type of invalid address code for the second requirement mentioned above.
According to the present invention, there is provided digital data apparatus wherein said data processing unit has first means for applying to the address bus, in order to address a peripheral unit, a particular address code corresponding to at least part of said multi-bit identification code for each peripheral unit. Said data processing unit also has second means for generating select signals and applying them to the peripheral units via said address bus, each respective peripheral unit being directly selected by its respective select signal, which respective select signal is a bit of one value in said part of the identification code. Said data processing unit also has third means for enabling said transfer of digital data upon establishing the presence of said respective peripheral unit selected by said respective select signal. The first, the second and the third means are all part of the data processing unit, and thus a decoder is no longer needed in the peripheral unit for uniquely selecting that peripheral unit. Each peripheral unit is uniquely selected by the same as the address code for the unit and by causing interrogation means to compare these two codes. Also, in the specific implementation of the digital data apparatus, the memory unit addresses comprise multi-bit address codes which are fed over an address bus to a decoder which in respect of each code produces a unique select signal for selecting a particular one of the memory units for interrogation. The provision of the decoder ensures that each address code does select uniquely only one memory unit (when provided).